News

Sage-DA on an industry experts panel at DAC

Posted on: May 30th, 2016

The Insanity of DRC Rules and DFM at 10nm and Below

A panel hosted by Si2 at DAC  June 6  11:00 am  Si2 booth 239

In just over 10 years, process nodes will shrink from 100nm in 2005 to 10nm in 2017. An upsurge in the complexity of advanced DRC decks makes it almost impossible to code rule decks using basic Pass/Fail DRC rules. The exponential increase in the design rule count and the number of operations required by complex DRC rules has made physical verification run times longer and increases debug times. A panel of four industry experts representing design, implementation, verification and manufacturing will describe their own personal experiences and best practices for developing DRC decks for 10nm processes.

Click here for more details.

News
15 June 2017
8 June 2017
8 June 2017
6 june 2016
4 June 2016
30 May 2016
19 May 2016
10 February 2016
27 August 2015
17 August 2015
11 June 2015
29 May 2015
26 May 2015
22 May 2015
16 March 2015
19 January 2015
17 November 2014
3 November 2014
16 October 2014
29 May 2014
28 May 2014
20 May 2014
22 April 2014
31 March 2014
14 March 2014
25 Feb 2014
18 Feb 2014
18 Feb 2014
6 Feb 2014
24 Jun 2013
20 Jun 2013
7 Jun 2013
31 May 2013
20 May 2013
9 May 2013
7 May 2013
6 May 2013
6 May 2013