News

Sage-DA will exhibit at DAC San Francisco,
June 2-4, booth #1423

Posted on: May 20th, 2014

iDRM  --  The Design Rule Compiler Platform  --  Booth 1423

Come and see how to develop and capture complex design rules as easy as in Powerpoint, and automatically create advanced design rule checks and queries in minutes without any programming.

Featured demonstrations             |Sign up here for a demo|

  • Graphical design rule capture and check
    for DR developers, PDK developers, designers
  • The no-programming, no error, easy approach to physical verification.
    Simply draw your design rule in a friendly GUI and press the button:  The rule you captured will now be checked on your design

  • Design rule analysis and layout data-mining
    for Technology, Yield, DFM and tape-out teams
  • Finding out and communicating what is actually in your design
    Get complete measurements and statistics on all instances of: specific design rules, sensitive patterns, device physical characteristics, layout dependent effects, DFM rules, etc.
    Auto-generate a complete report with all details, coordinates, tables & screen shots in seconds.

  • DRC deck verification and QA NEW
    for DRM teams , PDK and DRC developers
  • Automatic creation of QA pass/fail tests for verifying any DRC decks
    DRVerify generates an exhaustive set of pass/fail  test cases that exercise all "corner cases" of complex design rule parameters. All done automatically from the design rule definition and ensures complete coverage and correctness.  

  • DRM to PDK parametersNEW  
    for CAD teams, PDK developers
  • Automatic generation and update of Pcell physical parameters from the design rule manual

  • Custom Design Rule Checks:  
    for CAD teams, designers, product managers
  • Adding a set of design oriented rules and checks on top of the foundry DRC deck
    Additional design rules to ensure quality of design, optima performance, and minimized variability can be added easily and graphically – no programming required!

  • Automating std cell library layout for 14/16 nm   
    for library development & layout
  • nmigrate:  a 100% DRC-clean migration and correction tool for 14nm/16nm

nmigrate: the only tool available today for migrating, rule-updates or DRC-cleanup of libraries in 16nm and 14nm.  Handles all advanced design rules, including coloring, local interconnect and FinFET rules.

 

 - Sign up here for a demo -

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